1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, the present invention relates to charge pumps, phase change random access memories including charge pumps, and method of writing data into phase change random access memories.
A claim of priority is made to Korean Patent Application No. 10-2005-0104148, filed on Nov. 2, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to energy (e.g., thermal energy) so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
As with other types of semiconductor memories, efforts are being made to reduce the level of supply voltage used to drive PRAM devices. However, any reduction in supply voltage can make it difficult to generate sufficient write currents to reliably program the state of the phase-change material as discussed in the preceding paragraph. Further, in the case of low level supply voltages, the selection of phase change cells can become problematic due to voltage drops caused by parasitic resistance between the power supply voltage and the phase change memory cells.
As such, it may become necessary to rely on voltage boosting circuits when, for example, generating write currents for programming PRAM device. In this case, a boosted voltage is utilized to drive portions of the PRAM device. However, due to extremely small size of components making up a PRAM device, excess exposure to boosted voltages can adversely affect the overall reliability of the PRAM device. It is thus desirable to minimize the period of time during which internal circuits of the PRAM are exposed to high voltages.
It has been suggested to utilize a boosted voltage for write operations of the PRAM device, and to utilize a power supply voltage for other operations, such as read and standby operations. However, in this case, a charge pump is activated prior to each write operation in order to increase a drive voltage to the boosted voltage. This process takes time, and disadvantageously results in a delay in execution of the write operation.